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LM1276 150 mhz i 2 c compatible rgb preamplifier with internal 512 character osd rom, 512 character ram and 4 dacs general description the LM1276 pre-amp is an integrated cmos crt preamp with an integrated hi-brite window generator, 512 character osd generator, and an auto size measurement circuit. it has an i 2 c compatible interface, which allows control of all the parameters necessary to directly setup and adjust the gain and contrast in the crt display. brightness and bias can be controlled through the dac outputs, which are well matched to the lm2479 and lm2480 integrated bias clamp ics. the LM1276 preamp is also designed to be compatible with the lm247x high gain driver family. black level clamping of the video signal is carried out directly on the ac coupled input signal into the high impedance preamplifier input, thus eliminating the need for additional clamp capacitors. horizontal and vertical blanking of the outputs is provided. vertical blanking is optional and its duration is register programmable. the ic is packaged in an industry standard 28-lead narrow dip molded plastic package. features n integrated hi-brite window generator operation independent of the microcontroller. n programmable video emphasis control. n 8 programmable hi-brite windows. n hi-brite enhancement on full screen, window only, or outside of windows. n fully addressable 512 character osd. n internal 512 character osd rom usable as either (a) 384 2-color plus 128 4-color characters, (b) 640 2-color characters, or (c) some combination in between. n internal 512 character ram. n enhanced i 2 c compatible microcontroller interface to allow versatile page ram access. n osd window fade in/fade out. n osd variable tone transparency. n 3 bit osd contrast. n video data detection for auto centering & sizing. n 2 bit adjustable burn-in screen mode with no video input. n 4 dac outputs (8-bit resolution) for bus controlled crt bias and brightness. n spot killer, which blanks the video outputs when v cc falls below the specified threshold. n suitable for use with discrete or integrated clamp, with software configurable brightness mixer. n programmable abl onset for multi-limit applications. n 4-bit programmable start position for internal horizontal blanking. n horizontal blanking and osd synchronization directly from deflection signals. the blanking can be disabled, if desired. n vertical blanking and osd synchronization directly from sync signals. the blanking width is register programmable and can be disabled, if desired. n power saving mode with 65% power reduction. n matched to lm246x, lm247x drivers, and lm2479/80 bias ic?s. applications n ideal preamplifier ic for total hi-brite solution. n 17" and 19? bus controlled monitors with osd. n low cost systems with lm247x drivers. may 2005 LM1276 150 mhz i 2 c compatible rgb preamplifier with internal 512 character osd rom, 512 character ram and 4 dacs ? 2005 national semiconductor corporation ds200969 www.national.com
internal block diagram 20096961 figure 1. block diagram LM1276 www.national.com 2
internal block diagram (continued) 20096962 figure 2. LM1276 pinout order number LM1276aaa/na see ns package number n28d LM1276 www.national.com 3
absolute maximum ratings (notes 1, 3) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. supply voltage v cc , pins 10, 14, 17, and 22 6.0v peak video dc output source current (any one amp) pins 23, 24 or 25 1.5 ma voltage at any input pin (v in ) ?0.5v v in v cc +0.5v video inputs (pk-pk) 0.0v v in 1.2v thermal resistance to ambient ( ja ) 51?c/w power dissipation (p d ) (above 25?c derate based on ja and t j ) 2.4w thermal resistance to case ( jc ) 32?c/w junction temperature (t j ) 150?c esd susceptibility (note 4) 3.0 kv esd machine model (note 13) 350v storage temperature ?65?c to +150?c lead temperature (soldering, 10 sec.) 265?c operating ratings (note 2) temperature range 0?c to +70?c supply voltage v cc 4.75v v cc 5.25v video inputs (pk-pk) 0.0v v in 1.0v video signal electrical characteristics unless otherwise noted: t a = 25?c, v cc = +5.0v, v in = 0.70 v p-p ,v abl =v cc ,c l = 8 pf, video outputs = 2.0 v p-p . setting numbers refer to the definitions in table 1 . see (note 7) for min and max parameters and (note 6) for typicals. symbol parameter conditions min typ max units i s supply current test setting 1, both supplies, no output loading. see (note 8). 220 300 ma i s-ps supply current, power save mode test setting 1, both supplies, no output loading. see (note 8). 55 85 ma v o blk a-b typical video black level difference between normal video and hi-brite video. no ac input signal -50 0 tbd vdc v o blk a-b, ch-ch typical channel to channel video black level difference between normal video and hi-brite video. no ac input signal -50 0 50 vdc v o blk active video black level output voltage test setting 4, no ac input signal, dc offset register (0x8438) set to 0xd5. 1.2 vdc v o blk step active video black level step size test setting 4, no ac input signal. 100 mvdc v o max maximum video output voltage test setting 3, video in = 0.70 v p-p 4.0 4.3 v le linearity error test setting 4, staircase input signal (see (note 9)). 5% t r video rise time (note 5), 10% to 90%, test setting 4, ac input signal. 3.1 ns os r rising edge overshoot (note 5), test setting 4, ac input signal. 2% t f video fall time (note 5), 90% to 10%, test setting 4, ac input signal. 2.9 ns os f falling edge overshoot (note 5), test setting 4, ac input signal. 2% bw channel bandwidth (?3 db) (note 5), test setting 4, ac input signal. 150 mhz v sep 10 khz video amplifier 10 khz isolation (note 14), test setting 8. ?60 db v sep 10 mhz video amplifier 10 mhz isolation (note 14), test setting 8. ?50 db a v max maximum voltage gain test setting 8, ac input signal. 3.8 4.1 v/v a v c-50% contrast attenuation @ 50% test setting 5, ac input signal. ?5.2 db a v min/a v max maximum contrast attenuation (db) test setting 2, ac input signal. ?12 db LM1276 www.national.com 4
video signal electrical characteristics (continued) unless otherwise noted: t a = 25?c, v cc = +5.0v, v in = 0.70 v p-p ,v abl =v cc ,c l = 8 pf, video outputs = 2.0 v p-p . setting numbers refer to the definitions in table 1 . see (note 7) for min and max parameters and (note 6) for typicals. symbol parameter conditions min typ max units a v g-50% gain attenuation @ 50% test setting 6, ac input signal. ?4.0 db a v g-min maximum gain attenuation test setting 7, ac input signal. ?11 db a v match maximum gain match between channels test setting 3, ac input signal. 0.5 db a v track gain change between channels tracking when changing from test setting 8 to test setting 5. see (note 11). 0.5 db vid threshold video threshold normal operation 80 mv v abl th abl control range upper limit (note 12), test setting 4, ac input signal. 4.8 v v abl range abl gain reduction range (note 12), test setting 4, ac input signal. 2.8 v a v 3.5 /a v max abl gain reduction at 3.5v (note 12), test setting 4, ac input signal. v abl = 3.5v ?2 db a v 2.0 /a v max abl gain reduction at 2.0v (note 12), test setting 4, ac input signal. v abl = 2.0v ?12 db i abl max abl input current sink capability (note 12), test setting 4, ac input signal. 2.5 ma v abl max maximum abl input voltage during clamping (note 12), test setting 4, ac input signal. i abl =i abl max v cc + 0.1 v a v abl track abl gain tracking error (note 9), test setting 4, 0.7 v p-p input signal, abl voltage set to 4.5v and 2.5v. 5.0 % r ip minimum input resistance (pins 5, 6, 7) test setting 4. 20 m ? osd electrical characteristics unless otherwise noted: t a = 25?c, v cc = +5.0v. see (note 7) for min and max parameters and (note 6) for typicals. symbol parameter conditions min typ max units v osdhigh max maximum osd level with osd contrast 111 palette set at 111, osd contrast = 111, test setting 3 3.02 v v osdhigh 110 maximum osd level with osd contrast 110 palette set at 111, osd contrast = 110, test setting 3 2.91 v v osdhigh 101 maximum osd level with osd contrast 101 palette set at 111, osd contrast = 01, test setting 3 2.79 v v osdhigh 100 maximum osd level with osd contrast 100 palette set at 111, osd contrast = 100, test setting 3 2.67 v v osdhigh 011 maximum osd level with osd contrast 011 palette set at 111, osd contrast = 011, test setting 3 2.55 v v osdhigh 010 maximum osd level with osd contrast 010 palette set at 111, osd contrast = 010, test setting 3 2.43 v v osdhigh 001 maximum osd level with osd contrast 001 palette set at 111, osd contrast = 001, test setting 3 2.32 v v osdhigh 000 maximum osd level with osd contrast 000 palette set at 111, osd contrast = 000, test setting 3 2.20 v ? v osd (black) difference between osd black level and video black level (same channel) register 0x8438=0x18, input video = black, same channel, test setting 8 130 mv LM1276 www.national.com 5
osd electrical characteristics (continued) unless otherwise noted: t a = 25?c, v cc = +5.0v. see (note 7) for min and max parameters and (note 6) for typicals. symbol parameter conditions min typ max units ? v osd-black (track) difference between osd black level and video black level between any 2 channels register 0x8438=0x18, input video = black, same channel, test setting 8 115 mv ? v osd (white) output match between channels palette set at 111, osd contrast = 11, maximum difference between r, g and b 3% v osd-out (track) output variation between channels osd contrast varied from max to min 3% dac output electrical characteristics unless otherwise noted: t a = 25?c, v cc = +5.0v, v in = 0.7v, v abl =v cc ,c l = 8 pf, video outputs = 2.0 v p-p . see (note 7) for min and max parameters and (note 6) for typicals. dac parameters apply to all 4 dacs. symbol parameter conditions min typ max units v min dac min output voltage of dac register value = 0x00 0.5 0.7 v v max dac mode 00 max output voltage of dac register value = 0xff, dcf[1:0] = 00b 3.7 4.2 v v max dac mode 01 max output voltage of dac in dcf mode 01 register value = 0xff, dcf[1:0] = 01b 1.85 2.35 v ? v max dac (temp) dac output voltage variation with temperature 0 < t < 70?c ambient 0.5 mv/?c ? v max dac (v cc ) dac output voltage variation with v cc v cc varied from 4.75v to 5.25v, dac register set to mid-range (0x7f) 50 mv linearity linearity of dac over its range 5 % monotonicity monotonicity of the dac excluding dead zones 0.5 lsb i max max load current ?1.0 1.0 ma system interface signal characteristics unless otherwise noted: t a = 25?c, v cc = +5.0v, v in = 0.7v, v abl =v cc ,c l = 8 pf, video outputs = 2.0 v p-p . see (note 7) for min and max parameters and (note 6) for typicals. dac parameters apply to all 4 dacs. symbol parameter conditions min typ max units v vth+ vflyback positive switching guarantee vertical blanking triggered 2.0 v v spot spot killer voltage (note 17), v cc adjusted to activate 3.4 3.9 4.3 v v ref v ref output voltage (pin 2) 1.25 1.45 1.65 v v il (scl, sda) logic low input voltage ?0.5 1.5 v v ih (scl, sda) logic high input voltage 3.0 v cc + 0.5 v i l (scl, sda) logic low input current sda or scl, input voltage = 0.4v 10 a i h (scl, sda) logic high input voltage sda or scl, input voltage = 4.5v 10 a v ol (scl, sda) logic low output voltage i o = 3 ma 0.5 v f h min minimum horizontal frequency pll & osd functioning 25 khz f h max maximum horizontal frequency pll & osd functioning 110 khz i hfb in max horizontal flyback input current absolute maximum during flyback 5ma i in peak current during flyback design value 4 ma i hfb out max horizontal flyback input current absolute maximum during scan ?700 a i out peak current during scan not exact - duty cycle dependent ?550 a i in threshold i in h-blank detection threshold 0 a LM1276 www.national.com 6
system interface signal characteristics (continued) unless otherwise noted: t a = 25?c, v cc = +5.0v, v in = 0.7v, v abl =v cc ,c l = 8 pf, video outputs = 2.0 v p-p . see (note 7) for min and max parameters and (note 6) for typicals. dac parameters apply to all 4 dacs. symbol parameter conditions min typ max units t h-blank on h-blank time delay - on + zero crossing of i hfb to 50% of output blanking start. i 24 = +1.5ma 45 ns t h-blank off h-blank time delay - off ? zero crossing of i hfb to 50% of output blanking end. i 24 = ?100a 85 ns v blank max maximum video blanking level test setting 4, ac input signal 0 0.25 v f freerun free run h frequency, including h blank 42 khz t pw clamp minimum clamp pulse width see (note 15) 200 ns v clamp max maximum low level clamp pulse voltage video clamp functioning 2.0 v v clamp min minimum high level clamp pulse voltage video clamp functioning 3.0 v i clamp low clamp gate low input current v 23 = 2v ?0.4 a i clamp high clamp gate high input current v 23 = 3v 0.4 a t clamp-video time from end of clamp pulse to start of video referenced to blue, red and green inputs 50 ns note 1: limits of absolute maximum ratings indicate below which damage to the device must not occur. note 2: operating ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. note 3: all voltages are measured with respect to gnd, unless otherwise specified. note 4: human body model, 100 pf discharged through a 1.5 k ? resistor. note 5: input from signal generator: t r ,t f < 1 ns. note 6: typical specifications are specified at +25?c and represent the most likely parametric norm. note 7: datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. the guaranteed specifications apply only for the t est conditions listed. some performance characteristics may change when the device is not operated under the listed test conditions. note 8: the supply current specified is the quiescent current for v cc and 5v dig with r l = . load resistors are not required and are not used in the test circuit, therefore all the supply current is used by the pre-amp. note 9: linearity error is the maximum variation in step height of a 16 step staircase input signal waveform with a 0.7 v p-p level at the input. all 16 steps equal, with each at least 100 ns in duration. note 10: dt/dv cc = 200*(t 5.5v ?t 4.5v )/ ((t 5.5v +t 4.5v )) %/v, where: t 5.5v is the rise or fall time at v cc = 5.5v, and t 4.5v is the rise or fall time at v cc = 4.5v. note 11: ? a v track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. it is the difference in gain change between any two amplifiers with the contrast set to a v c?50% and measured relative to the a v max condition. for example, at a v max the three amplifiers? gains might be 12.1 db, 11.9 db, and 11.8 db and change to 2.2 db, 1.9 db and 1.7 db respectively for contrast set to a v c?50%. this yields a typical gain change of 10.0 db with a tracking change of 0.2 db. note 12: the abl input provides smooth decrease in gain over the operational range of 0 db to ?5 db: ? a abl = a(v abl =v abl max gain )?a(v abl = v abl min gain ). beyond ?5 db the gain characteristics, linearity and pulse response may depart from normal values. note 13: machine model esd test is covered by specification eiaj ic-121-1981. a 200 pf cap is charged to the specific voltage, then discharged directly into the ic with no external series resistor (resistance of discharge path must be under 50 ? ). note 14: measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. terminate the undriven amplifier inputs to simulate generator loading. repeat test at f in = 10 mhz for v sep 10 mhz. note 15: a minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 khz. this limit is guaranteed by design. if a lower line rate is used then a longer clamp pulse may be required. note 16: adjust input frequency from 10 mhz (a v max reference level) to the ?3 db corner frequency (f ?3 db ). note 17: once the spot killer has been activated, the LM1276 remains in the off state until v cc is cycled (reduced below 0.5v and then restored to 5v). hexadecimal and binary notation hexadecimal numbers appear frequently throughout this document, representing slave and register addresses, and register values. these appear in the format ?0x...?. for ex- ample, the slave address for writing the registers of the LM1276 is hexadecimal ba, written as 0xba. on the other hand, binary values, where the individual bit values are shown, are indicated by a trailing ?b?. for example, 0xba is equal to 10111010b. a subset of bits within a register is referred to by the bit numbers in brackets following the register value. for example, the osd contrast bits are the fourth, fifth, and sixth bits of register 0x8538. since the first bit is bit 0, the osd contrast register is 0x8538[5:3]. register test settings table 1 shows the definitions of the test settings 1?8 re- ferred to in the specifications sections. each test setting is a combination of five hexadecimal register values, contrast, gain (blue, red, green) and dc offset. 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register test settings (continued) table 1. test settings control no. of bits test settings 1234 5678 contrast 7 0x7f (max) 0x00 min 0x7f (max) 0x7f (max) 0x40 (50.4%) 0x7f (max) 0x7f (max) 0x7f (max) b, r, g gain 7 0x7f (max) 0x7f (max) 0x7f (max) set v o to 2v p-p 0x7f (max) 0x40 (50.4%) 0x00 (min) 0x7f (max) dc offset 3 0x00 (min) 0x05 0x07 (max) 0x05 0x05 0x05 0x05 0x05 LM1276 www.national.com 8
osd vs video intensity the osd amplitude has been increased over the lm1237 level. during monitor alignment the three gain registers are used to achieve the desired front of screen color balance. this also causes the osd channels to be adjusted accord- ingly, since these are inserted into the video channels prior to the gain attenuators. this provides the means to fine-tune the intensity of the osd relative to the video as follows. if a typical starting point for the alignment is to have the gains at maximum (0x7f) and the contrast at 0x55, the resultant osd intensity will be higher than if the starting point is with the gains at 0x55 and the contrast at maximum (0x7f). this tradeoff allows the fine-tuning of the final osd intensity relative to the video. in addition, the osd contrast register, 0x85c8[5:3], provides 8 major increments of intensity. to- gether, these allow setting the osd intensity to the most pleasing level. esd protection the LM1276 features a 3.0 kv esd protection level (see (notes 4, 13)). this is provided by special internal circuitry, which activates when the voltage at any pin goes beyond the supply rails by a preset amount. this protection is applied to all the pins, including sda and scl. LM1276 www.national.com 9
typical performance characteristics v cc = 5v, t a = 25?c unless otherwise specified 20096902 figure 3. logic horizontal blanking 20096903 figure 4. logic vertical blanking 20096904 figure 5. deflection horizonal blanking 20096906 figure 6. logic clamp pulse 20096907 figure 7. red cathode response 20096908 figure 8. abl gain reduction curve LM1276 www.national.com 10
typical performance characteristics v cc = 5v, t a = 25?c unless otherwise specified (continued) system interface signals the horizontal sync, flyback, vertical sync, and the clamp input signals are important for proper functionality of the LM1276. both blanking inputs must be present for osd synchronization. in addition, the horizontal blanking input also assists in setting the proper cathode black level, along with the clamping pulse. the vertical blanking input initiates a blanking level at the LM1276 outputs, which is program- mable from 3 to 127 lines (at least 10 is recommended). this input is set up to only accept a vertical sync pulse, and the leading edge is used to start the programmable vertical blanking signal directly. the start position of the internal horizontal blanking pulse is programmable from 0 to 64 pixels ahead of the start position of the horizontal flyback input. both horizontal and vertical blanking can be individu- ally disabled, if desired. figure 3 and figure 4 show the horizontal flyback input when it is logic level and the vertical input (which must always be logic level). figure 3 shows the smaller pin 28 voltage superimposed on the horizontal blanking pulse input to the neck board with r h = 4.7k and c 1 = 0.1 f. note where the voltage at pin 28 is clamped to about 1v when the pin is sinking current. figure 4 shows the smaller pin 1 voltage superimposed on the vertical blanking input to the neck board with r v = 4.7k. these component values corre- spond to the application circuit of figure 9 . please note that the horizontal flyback signal to pin 28 must be continuously provided to the ic, even during en- ergy save or sleep modes. in the application, this signal should be always generated whether the vga cable is dis- connected, the monitor is in energy save mofe, or sleep mode. figure 5 show the case where the horizontal input is from deflection. figure 5 shows the pin 28 voltage which is de- rived from a horizontal flyback pulse of 35v peak to peak with r h = 8.2k and c 1 jumpered. figure 6 shows the pin 27 clamp input voltage superimposed on the neck board clamp logic input pulse .r=1kand should be chosen to limit the pin 27 voltage to about 2.5v peak to peak. this corresponds to the application circuit given in figure 9 . the clamp input pin can also be internally con- nected to the horizontal sync pin, thus eliminating the need for a clamp signal supplied to the neckboard. this can be enabled with register 0x853e[4]. h sync & v sync v sync at pin 1 and h sync at pin 15 must be supplied with logic level signals generated by the mcu. in an application where a logic level clamp pulse is used, the same signal can be used for the h sync input. it is important that both v sync and h sync are always receiving signals, even during vga cable disconnect, energy save mode, or sleep mode. cathode response figure 7 shows the response at the red cathode for the application circuit in figures 9, 10 . the input video rise time is 1.5 ns. the resulting leading edge has a 7.1 ns rise time and 7.6% overshoot, while the trailing edge has a 7.1 ns rise time and 6.9% overshoot using an lm2467 driver. abl gain reduction the abl function reduces the contrast level of the LM1276 as the voltage on pin 26 is lowered from v cc to around 2v. figure 8 shows the amount of gain reduction as the voltage is lowered from v cc (5.0v) to 2v. the gain reduction is small until v 26 reaches the knee around 3.7v, where the slope increases. many system designs will require about 3 db to 5 db of gain reduction in full beam limiting. additional attenu- ation is possible, and can be used in special circumstances. however, in this case, video performance such as video linearity and tracking between channels will tend to depart from normal specifications. the onset of abl in the LM1276 is adjustable so that the amount of beam limiting can be varied, especially for larger hi-brite window displays where the contrast level is not desired to be reduced as much as a normal video display. the beam current limiting is 4-bit adjustable in steps of 80 a each all the way up to a delta of 1.2 ma. the value of the abl pull up resistor (r2) to the external +80v supply must be selected carefully such that the abl threshold current will be at the desired maximum (i.e. 2 ma) when register 0x85c4 is at the lowest setting, 0x00. there are 4 different abl current registers corresponding to 4 different abl settings. each setting or register (0x85c4 - 0x85c7) can be assigned a different abl current threshold. abl current register 0 can correspond to a minimal area of the screen being highlighted, and abl current register 4 can correspond to the maximum area of the screen being high- lighted. this area is calculated by the hibrite software, and the particular abl register that is is to be activated is se- lected by the software. the values of each register are written by the mcu. LM1276 www.national.com 11
typical performance characteristics v cc =5v,t a = 25?c unless otherwise specified (continued) video processing emphasis, center frequency at maximum 20096963 center frequency, emphasis at maximum 20096964 these two plots show the processing done by the LM1276 on the video input signal. there are two variables for the video processing, emphasis and center frequency. empha- sis is controlled by bits 0-2 in registers 0x85c8, 0x85ca, or 0x85cc. this gives 8 different levels of emphasis. in the top plot the center frequency is set at its maximum level and the 8 different levels of emphasis are measured. the video with no emphasis is adjusted to a 0.7 v p-p level. using maximum emphasis the video is increased to a 0.9 v p-p level at the rising edge of the video. if the falling edge was measured it would show a similar waveform, but going in the negative direction. center frequency is shown in the bottom plot. control of the center frequency is done with bits 4-7 in register 0x85c1 . this gives 16 adjustments for this feature. every other adjustment is shown in the bottom plot, since showing all 16 adjustments would have made the plot too difficult to read. the curves closely approximate the peaking of an rc network. therefore, the term center frequency means the rc time constant that is approximated by each curve in the above plot. a true rc peaking network would give very large overshoot. the LM1276 has special circuitry to clip the very large overshoot, yet has the complete benefit of the rc peaking. this special circuitry allows for much more over- shoot than one could do with rc peaking and still not saturate the video channel. note that the video channel with the emphasis also has its own independent contrast control. this allows the user to adjust his monitor for a brighter picture within the hi-brite window and optimize the emphasis for the resolution he is using with the monitor. now, the monitor user can give his pictures or video a special ?sparkle? when using the capa- bilities of the LM1276. osd phase locked loop the pll in the LM1276 serves both the osd as well as the hi-brite window generation. the pixels per line range for the LM1276 osd is from 704 to 1152 pixels per line, in incre- ments of 64. the maximum osd pixel frequency available is 111 mhz. for example, if the horizontal scan rate is 106 khz, 1024 pixels per line would be acceptable to use, since the osd pixel frequency is: horizontal scan rate x ppl = 106khz x 1024 = 108.5 mhz if 1152 pixels per line is being used, the horizontal scan rate would have to be lower than 106 khz in order to not exceed the maximum osd pixel frequency of 111 mhz. the maxi- mum number of video lines that may be used is 1536 lines as in a 2048x1536 display. at this line rate, using a ppl setting of 4 is recommended. the LM1276 has a pll auto feature, which will automatically select an internal pll frequency range setting that will guarantee optimal osd locking for any horizontal scan rate and for improved jitter performance over a wider temperature range. this eliminates the need for pll register settings determined by the user, as well as improved pll performance. to initialize the pll auto feature, set bit, 0x8439[4] to 1. this will effectively perform all necessary calibrations and activate the pll auto mode, which takes approximately 2?4 vertical scan period to complete, and must be done while the video is blanked. table 2 shows the recommended horizontal scan rate ranges (in khz) for each pixels per line register setting, 0x8401[7:5]. these ranges are recommended for chip ambient temperatures of 0 o cto 70 o c, and the recommended pll filter values are 6.2 k ? , 0.01 uf, and 1000 pf. while the osd pll will lock for other register combinations and at scan rates outside these ranges, the performance of the loop will be improved if these recommendations are followed. pll auto mode initialization sequence blank video. set 0x8539[4] to 1. wait for at least 2?4 vertical periods or vertical sync pulses to pass. unblank video. this sequence must be done by the microcontroller at sys- tem power up, as well as each time there is a horizontal line rate change from the video source, for the pll auto mode to function properly. LM1276 www.national.com 12
typical performance characteristics v cc =5v,t a = 25?c unless otherwise specified (continued) table 2. osd register recommendations ppl=0 ppl=1 ppl=2 ppl=3 ppl=4 ppl=5 ppl=6 ppl=7 pll auto 25 - 61 25 - 53 25 - 98 25 - 110 25 - 110 25 - 108 25 - 102 25 - 96 pin descriptions and application information pin no. pin name schematic description 1 v sync logic level vertical sync signal received from the video card in the pc or sync stripper circuit. 2 4 analog v cc analog ground ground pin and power supply pin for the input analog portion of the LM1276. note the recommended charge storage and high frequency capacitors, which should be as close to pins 2 and 4 as possible. 3v ref r ext external current set resistor, 10k 1%, sets the internal bias current level for optimum performance of the LM1276. this resistor should be placed as close to pin 3 and the pin 4 ground return as possible. 5 6 7 blue video in red video in green video in these video inputs must be ac coupled with a .0047 f cap. internal dc restoration is done at these inputs. a series resistor of about 33 ? and external esd protection diodes should also be used for protection from esd damage. 8 9 pll ground pll filter recommended topology and values are shown to the left. it is recommended that both filter branches be bypassed to the independent ground as close to pin 8 as possible. great care should be taken to prevent external signals from coupling into this filter from video, i 2 c, etc. LM1276 www.national.com 13
pin descriptions and application information (continued) pin no. pin name schematic description 10 pll v cc the ground pin should be connected to the rest of the circuit ground by a short but independent pcb trace to prevent contamination by extraneous signals. the pll v cc pin should be isolated from the rest of the v cc line by a ferrite bead and bypassed to pin 8 with an electrolytic capacitor and a high frequency ceramic. 11 14 digital ground digital v cc ground pin and power supply pin for the digital portion of the LM1276. note the recommended charge storage and high frequency capacitors, which should be as close to pins 11 and 14 as possible. 12 scl the i 2 c compatible clock line. a pull-up resistor of about 2.2 k ? should be connected between this pin and v cc . a resistor of at least 100 ? should be connected in series with the clock line for additional esd protection. 13 sda the i 2 c compatible data line. a pull-up resistor of about 2.2 k ? should be connected between this pin and v cc . a resistor of at least 100 ? should be connected in series with the data line for additional esd protection. 15 h sync logic level horizontal sync signal received from the mcu or sync stripper circuit. this input can also be derived from the clamp input as long as it is a logic level signal. 16 17 digital ground digital v cc ground pin and power supply pin for the digital portion of the LM1276. note the recommended charge storage and high frequency capacitors, which should be as close to pins 16 and 17 as possible. LM1276 www.national.com 14
pin descriptions and application information (continued) pin no. pin name schematic description 18 19 20 dac 3 output dac 2 output dac 1 output dac outputs for cathode cut-off adjustments and brightness control. the dac values are set through the i 2 c compatible bus. a resistor of at least 1k ? should be connected in series with these outputs for additional esd protection. 21 22 analog ground analog v cc ground pin and power supply pin for the output analog portion of the LM1276. note the recommended charge storage and high frequency capacitors which should be as close to pins 21 and 22 as possible. 23 24 25 green output red output blue output these are the three video output pins. they are intended to drive the lm2476 and lm246x family of cathode drivers. nominally, about 2v peak to peak will produce 40v peak to peak of cathode drive. 26 abl the automatic beam limiter input is biased to the desired beam current limit by r abl and v bb and normally keeps d int forward biased. when the current resupplying the crt capacitance (averaged by c abl ) exceeds this limit, then d int begins to turn off and the voltage at pin 26 begins to drop. the LM1276 then lowers the gain of the three video channels until the beam current reaches an equilibrium value. 27 clamp this pin accepts either ttl or cmos logic levels. this pin can also be internally connected to the horizontal sync pin. the internal switching threshold is approximately one-half of v cc .an external series resistor, r, of about 1k is recommended to avoid overdriving the input devices. in any event, r must be large enough to prevent the voltage at pin 27 from going higher than v cc or below gnd. LM1276 www.national.com 15
pin descriptions and application information (continued) pin no. pin name schematic description 28 h flyback proper operation requires current reversal. r h should be large enough to limit the peak current at pin 28 to about +4 ma during blanking, and ?500 a during scan. c 1 is usually needed for logic level inputs and should be large enough to make the time constant, r h c 1 significantly larger than the horizontal period. r 1 and c 2 are typically 300 ? and 330 pf when the flyback waveform has ringing and needs filtering. c 3 may be needed to filter extraneous noise and can be up to 100 pf. LM1276 www.national.com 16
schematic diagram 20096924 figure 9. LM1276/lm2476 demo board schematic LM1276 www.national.com 17
schematic diagram 20096925 figure 10. LM1276/lm2476 demo board schematic (continued) LM1276 www.national.com 18
pcb layout 20096970 figure 11. LM1276/lm2476 demo board layout LM1276 www.national.com 19
burn in screen the LM1276 provides a burn in screen feature, where a full screen of white video will be displayed without the need for any video input. the burn in screen is enabled by setting bit 5 of register 0x8439 to 1. the contrast level of this burn in display can be adjusted wit h a 2 bit dac over the range of 65% to 85% of normal white level video. this adjustment is made with register 0x8439[7:6]. programmable horizontal blank the leading edge position of the internal horizontal blank can be programmed with respect to the horizontal flyback zero crossing leading edge in steps of 1 osd pixel up to a maximum of 31 steps as shown below in figure 12 . this start position of the horizontal blanking pulse is only pro- grammable to occur before the horizontal flyback zero cross- ing edge, and cannot be programmed in the opposite direc- tion. the trailing edge of the horizontal blanking pulse is independent of the programmable leading edge, and its relativity to the horizontal flyback trailing edge remains un- changed. to use this feature, both horizontal blanking ( 0x843a[0] ) and programmable horizontal blanking ( 0x843a[2] ) must be enabled. the number of steps is pro- grammed with the bits in 0x843a[7:3] . when this feature is disabled, please refer to the h-blank time delay ? on specification (+ zero crossing of i hfb to 50% of output blanking end) listed under the system interface signal char- acteristics section. video detection for auto-sizing & auto-centering the LM1276 is capable of taking measurements necessary for the monitor?s microcontroller to perform the auto-sizing and auto-centering operations. the horizontal and vertical flybacks/syncs are used as the reference for timing. either the flyback or sync signals may be used. in this section, the flyback signals will be considered, although horizontal and vertical sync can be applied similarly. the resultant outputs are the flyback time, the position of the start of video relative to the flyback end, and the time from the end of the active video to the start of the flyback time. since the total line time is known, the microcontroller can calculate the active video time. the microcontroller can center the video between the start and end of flyback for best image centering, and to calculate the duty cycle of the video with respect to the forward scan time, thus giving a measure of the relative size of the image. video input detection the LM1276 will detect even low-level video information to determine the video image size and position. the video detect logic must also find the extreme points of the dis- played image during each frame with respect to the horizon- tal and vertical flyback pulses as measured using the internal pll. for best performance in the auto-sizing mode, it is recommended that the application use the maximum pixels per line mode is used when measurements are made. the durations to be measured are shown generically in figure 13 and apply to both horizontal and vertical timings. since measurements are made in terms of osd pixels, the ratio of osd pixels per line to the video pixels per line must be applied to the data below to attain measure- ments in terms of video pixels. 1. flyback or sync period: the duration of either the sync input or the horizontal flyback, in either horizontal lines (vertical) or pixels (horizontal). 2. back porch period: the duration between the trailing edge of the sync or flyback pulse and the leading edge of the first detected video, in either lines (vertical) or pixels (horizontal). 3. front porch: the duration between the trailing edge of the last detected video and the leading edge of the sync or flyback pulse, in either lines (vertical) or pixels (hori- zontal). the video period is the duration between the leading edge of the first detected video and the trailing edge of the last detected video, in either lines (vertical) or osd pixels (hori- zontal). this period is calculated by the microcontroller with the measured periods above. as the video may start and finish at different positions on the screen, depending upon the image, the measured horizontal porches and video time may vary from line to line. to over- come this, the periods should be measured over at least one entire field. the hardware records the shortest back porch and front porch periods used over the measured period. the possible error for the above measurements are within 1 to 2 osd pixels. the video period is the duration between the leading edge of the first detected video and the trailing edge of the last detected video, in either lines (vertical) or osd pixels (hori- zontal). this period is calculated by the microcontroller with the measured periods above. the analog front end video detection is also utilized by the video data interface for decoding of color bar data. it is critical to note again that the threshold for video detec- tion is 80mv above the internal v ref voltage, and also the minimum rise time requirement of the driving pc video card must be at least 10.0ns. excessively slow rise times in the pc video card will prevent the video detect circuit from working properly. to perform an auto size calculation, the following instruction sequence must be done by the mcu: 20096952 figure 12. programmable internal h. blank LM1276 www.national.com 20
video detection for auto-sizing & auto-centering (continued) auto size calculation instruction sequence set register bits 0xfff8[5] and 0xfff8[4] to high set register bits 0xfffd[3] to low set register bit 0x8400[6] to high wait for 0x8400[7] to become high by itself when 0x8400[7] is high, then read auto size data regis- ters 0x8580 to 0x858f set register bits 0xfffd[3] to high set register bits 0xfff8[5] and 0xfff8[4] to low pll lock detect and horizontal input select during the monitor initialization routine by the mcu, register bit 0xfffd[3] must be set high. this bit is only set low during osd display operation and auto size calculations. please see the instructions above for auto size calculations. the following sequence which involves register 0xfffd and 0xfff8 must be done by the mcu when the osd is en- abled. register bits, 0xfff8[5:4], control the pll lock detect override function. before writing to memory to setup the osd, or enabling osd: set register bit 0x8400[0] to high set register bits 0xfff8[5] and 0xfff8[4] to high set register bits 0xfffd[3] to low initialize osd and write to memory set register bits 0x8400[1] and/or 0x8400[2] to high before disabling osd: set register bits 0x8400[1] and/or 0x8400[2] to low set register bits 0xfffd[3] to high set register bits 0xfff8[5] and 0xfff8[4] to low set register bit 0x8400[0] to low please see the osd programming section for more detailed information or displaying osd pages and accessing the ram hi-brite video enhancement functional description the LM1276 enables a desired area of the crt monitor display to be enhanced for vivid tv quality images. the LM1276 along with the software that is provided by national semiconductor is fully self-sufficient and independent of the microcontroller in generating and controlling hi-brite win- dows. hi-brite video processing the enhancement is achieved with programmable empha- sis, programmable center frequency, and an additional con- trast adjustment control that is separate from the normal video contrast control of the preamp. having an indepen- dent contrast control allows the user to adjust the video gain normally, having the higher gain to have a ?brighter? picture within the hi-brite window. the emphasis control is used to give more ?sparkle? to the highlighted video. video that is processed by the emphasis control has peaking added to the video. both the amplitude and the duration of the peaking are adjustable through the nsc software, optimizing the emphasis for different video resolutions. maximum peaking is 20%. emphasis emphasis is the amount of overshoot on the video signal. referring to figure 14 the overshoot is the ratio of the overshoot voltage to the video level after the emphasis has settled out of the output signal. the typical overshoot is about 20%. the peak measurement is taken 9 ns from the rising edge. this delay gives a more accurate peak mea- surement by avoiding any ringing that may occur at the rising edge. overshoot is defined in percent as: 20096953 figure 13. timing intervals LM1276 www.national.com 21
hi-brite video enhancement functional description (continued) bits 0 to 2 in registers 0x85c8, 0x85ca, or 0x85cc control the emphasis. when a ?4? is programmed into these bits the overshoot is typically 11%. a ?0? will give no overshoot in the hi-brite window. center frequency shown in figure 15 is how the center frequency is mea- sured. the center frequency is expressed as the time it takes the overshoot to settle to within 5% of the dc level of the pulse. bits 4 to 7 in register 0x85c1 control the center frequency. when an ?8? is programmed into 0x85c1[7:4] the t center freq is typically 80 ns. an ?f? will give about 145 ns. a ?0? will give no emphasis in the hi-brite window. hi-brite user modes there are 3 different modes whose settings are to be preset by the mcu. text mode, movie mode, and picture mode each have their own hibrite contrast and overshoot regis- ters (see the preamp interface registers table). when the user selects a particular mode, the preset register settings of that mode become in effect. there is also a 4th mode, which is the custom mode. the custom mode, however can be adjusted by the user through the hibrite software, and is not preset by the mcu. these modes can only be selected or changed from one to another through the hibrite software. there is no i 2 c register to select the effective mode. the default mode for the LM1276 is the movie mode. thus, the contrast and overshoot settings that will be in effect when a window is initially drawn or when the full screen hibrite function is called will be that of the settings preset for the movie mode. full screen hi-brite the LM1276 is capable of applying hibrite on the entire screen without the need for software. in the absence of software, this provides an alternative means of achieving emphasis and contrast boost on the picture through i 2 c. the contrast setting and overshoot that will be applied when this function is enabled will be that of the previously selected user mode, during the last instance that the software was in operation. for example, if the user last selected the picture mode in the software preference menu, before exiting the program, then the subsequent enabling of the full screen function through i 2 c will result in the picture mode settings being in effect on the full screen. the i 2 c bits that enable this function are 0x8590[5:4]. setting 0x8590[5] high will disable the hibrite window generation circuit that works together with the software, and 0x8590[4] enables the full screen hibrite. the window generation circuit must be shut off by 0x8590[5] in order for 0x8590[4] to have an effect. thus, to activate the full screen feature, simply set 0x8590[5:4] to high, and to deactivate, set 0x8590[5:4] to low. hi-brite window generation options up to 8 separate windows can be drawn and enabled simul- taneously, with programmable sizes and coordinates. the hi-brite video enhancement can also be applied to the entire desktop rather than to a specific window area or it can be applied to everything outside of the drawn window(s). all of this window programming can be achieved with national semiconductor?s software, and does not require any inter- facing with a microcontroller. 20096972 figure 14. overshoot measurement 20096973 figure 15. center frequency measurement LM1276 www.national.com 22
osd generator operation page operation figure 16 shows the block diagram of the osd generator. osd screens are created using any of the 512 predefined characters stored in the mask programmed rom. the LM1276 offers a full 9-bit character code operation, which allows the entire 512 rom character set to be displayed at once. the 9-bit character code operation enables all 512 character addresses to be independently accessed on one page. osd rom configuration the osd rom is equivalent to two 256 character roms of the type used in the lm1253a and lm1237. each rom can be considered as a group of 3 banks, (192) two-color char- acters followed by 1 bank (64) four-color characters. physi- cally, the combined rom is then 192x2 + 64x4 + 192x2 + 64x4. end-of-line and end-of-screen codes please refer to the lm1247 datasheet for details. blank character requirement five of the 512 character rom should be reserved as blank. rom addresses 0 and 1 are for the use of the end-of- screen and end-of-line characters as mentioned above. rom addresses 32, 63, and 511 must be reserved for test engineering purposes. all other rom addresses are usable, and any that are unused must be filled with at least a duplicate character. any other addresses except for those listed above should not be left blank. displaying an osd image consecutive lines of characters make up the displayed win- dow. these characters are stored in the page ram through the i 2 c compatible bus. each line can contain any number of characters up to the limit of the displayable line length (de- pendent on the pixels per line register), although some re- strictions concerning the enhanced features apply on char- acter lines longer than 32 characters. the number of characters across the width and height of the page can be varied under i 2 c compatible control, but the total number of characters that can be stored and displayed on the screen is limited to 512 including any end-of-line and end-of-screen characters. the horizontal and vertical start position can also be programmed through the i 2 c compatible bus. windows please refer to the lm1247 datasheet for details. osd video dac the gain of the osd dac is now programmable b ya3bit osd contrast register, for 8 levels. 20096927 figure 16. osd generator block diagram LM1276 www.national.com 23
osd generator operation (continued) osd video timing please refer to the lm1247 datasheet for details. character cell please refer to the lm1247 datasheet for details. four color font as two 2-color please refer to the lm1247 datasheet for details. attribute tables each character has an attribute value assigned to it in the page ram. the attribute value is 4 bits wide, making each character entry in the page ram 13 bits wide in total. the attribute value acts as an address, which points to one of 16 entries in either the two-color attribute table ram or the four-color attribute table ram. the attribute word in the table contains the coding information which defines which color is represented by color 0 and color 1 in the two color attribute table and color 0, color 1, color 2, color 3 in the four-color attribute table. each color is defined by a 9-bit value, with 3 bits assigned to each channel of rgb. a dynamic look-up table defines each of the 16 different color ?palettes?. as the look-up table can be dynamically coded by the microcontrol- ler over the i 2 c compatible interface, each color can be assigned to any one of 2 9 (i.e. 512) choices. this allows a maximum of 64 different colors to be used within one page using the 4-color characters, with up to 4 different colors within any one character and 32 different colors using the 2-color characters, with 2 different colors within any one character. transparent disable in addition to the 9 lines of video data, a tenth data line is generated by the transparent disable bit. when this line is activated, the black color code will be translated as ?trans- parent? or invisible. this allows the video information from the pc system to be visible on the screen when this is present. note that this feature is enabled on any black color in any of the first 8 attribute table entries. variable tone transparency when the transparency is already in effect the tone of the transparency can be adjusted. the contrast of the pc video that is visible in the ?transparent area? can be varied from 100% (fully transparent) to 0% (completely black). for ex- ample, 50% reduction in contrast would provide a semi- transparent effect. just as in the conventional transparency mode, variable tone transparency is effective on back- grounds or foregrounds with black color codes from only the first 8 attribute table entries. this feature is controlled by 0x85c0[6:0], and is only available when the transparency mode is already enabled. osd window fade in/fade out the osd window can be opened and closed with a fade in/fade out effect. the interval for fading in and fading out the osd window in the horizontal and vertical direction is vari- able and can be set by the microcontroller. this allows the osd window to be opened or closed in the vertical direc- tions, horizontal direction, or from the upper left to lower right corner. assuming the desired time to typically complete a full fade in or fade out is 0.5 seconds, and if the vertical scan frequency is for example, 60 hz, the number of steps is: with a typical osd window that is 300 pixels wide and 180 video lines long, the horizontal and vertical intervals would be: for a smooth fade in or fade out animation from the upper left corner to the lower right corner, the horizontal to vertical interval ratio must be matched to the aspect ratio of the osd window. in the example above, the 300 pixel wide by 180 lines long osd window has an aspect ratio of 5:3. thus, the horizontal to vertical interval ratio should be set to 5/3 or 10/6. with an osd window aspect ratio of 3:2, the h/v intervals can be set to 3/2, 6/4, 9/6, 12/8, or 15/10 for optimal operation. if the calculated aspect ratio of an osd window is a non-integer ratio, the h/v interval ratio should meet or exceed the aspect ratio. for example, if the osd aspect ratio is 3.7:2 (or 1.85:1), the h/v intervals should be set to 2/1, 4/2, 6/3, 8/4, 10/5, or 12/6. the fade in/out speed increases as h/v interval settings are increased. the osd window can also be faded in or out in only one direction if desired, by setting the horizontal interval to 0 for fading in/out strictly in the vertical direction or setting the vertical interval to 0 for fading in/out in the horizontal direction. in interlaced video formats, it is not recommended to fade in and fade out the osd in the vertical direction, and should be only faded in the horizontal direction. the fade in/out function can be enabled/disabled with bit 5 of the frame control register, 0x8400, and the horizontal & vertical intervals are controlled by setting register 0x8429. the osd window fade in/out feature can only be used with osd window 1. enhanced features please refer to the lm1247 datasheet for details. microcontroller interface the microcontroller interfaces to the LM1276 preamp using the i 2 c compatible interface. the protocol of the interface begins with a start pulse followed by a byte comprised of a 7-bit slave device address and a read/write bit. since the first byte is composed of both the address and the read/write bit, the address of the LM1276 for writing is 0xba (10111010b) and the address for reading is 0xbb (10111011b). the development software provided by na- tional semiconductor will automatically take care of the dif- ference between the read and write addresses if the target address under the communications tab is set to 0xba. fig- ures 17, 18 show a write and read sequence on the i 2 c compatible interface. write sequence the write sequence begins with a start condition, which consists of the master pulling sda low while scl is held high. the slave device write address, 0xba, is sent next. each byte that is sent is followed by an acknowledge bit. when scl is high, the master will release the sda line. the slave must pull sda low to acknowledge. the register to be LM1276 www.national.com 24
microcontroller interface (continued) written to is next sent in two bytes, the least significant byte being sent first. the master can then send the data, which consists of one or more bytes. each data byte is followed by an acknowledge bit. if more than one data byte is sent, the data will increment to the next address location. see figure 17 . read sequence read sequences are comprised of two i 2 c compatible trans- fer sequences: the first is a write sequence that only trans- fers the two byte address to be accessed. the second is a read sequence that starts at the address transferred in the previous address only write access and increments to the next address upon every data byte read. this is shown in figure 18 . the write sequence consists of the start pulse, the slave device write address (0xba), and the acknowl- edge bit; the next byte is the least significant byte of the address to be accessed, followed by its acknowledge bit. this is then followed by a byte containing the most signifi- cant address byte, followed by its acknowledge bit. then a stop bit indicates the end of the address only write access. next the read data access will be performed beginning with the start pulse, the slave device read address (0xbb), and the acknowledge bit. the next 8 bits will be the read data driven out by the LM1276 preamp associated with the ad- dress indicated by the two address bytes. subsequent read data bytes will correspond to the next increment address locations. data should only be read from the LM1276 when both osd windows and the fade in/ fade out are disabled. LM1276 address map 20096938 figure 17. i 2 c compatible write sequence 20096939 figure 18. i 2 c compatible read sequence LM1276 www.national.com 25
LM1276 address map (continued) character rom the 512 font characters from 0x0000 to 0x7fff can be read from rom by addressing the individual pixel rows of the desired character. since the characters have 12 columns, it takes two bytes to read a given row of pixels within one character. since the characters have 18 rows, a total of 36 bytes are needed to read the entire character. the 16-bit address for reading a row of pixels is formed as follows: address = (n * 0x1000) + (i * 0x40) + (r * 0x02) + h where: n = bank number (0x0 n 0x7) i = character index within its respective bank (0x00 i 0x3f) r = row of pixels within the character (0x00 r 0x11) h = 0 for low byte, 1 for high byte note that bit 0 of the character font access register, 0x8402, needs to be set to 0 to read the 2-color fonts. in order to read the four-color fonts, two complete reads are needed. set bit 0 of the character font access register, 0x8402, t oa0to read the least significant plane and t oa1to read the most significant plane. see table 3 . table 3. character rom addressing address range r/w description 0x8402[0] n 0x0000?0x2fff r these are the first 3 banks of two-color, read-only rom character fonts. there are 192 total characters in this range. 0 0x0 0x1 0x2 0x3000?0x3fff r this is bank 3 of four-color, read-only rom character fonts. there are 64 total characters in this range. 0/1 0x3 0x4000?0x6fff r these are banks 4, 5 and 6 of two-color, read-only rom character fonts. there are 192 characters in this range. 0 0x4 0x5 0x6 0x7000?0x7fff r this is bank 7 of four-color, read-only rom character fonts. there are 64 total characters in this range. 0/1 0x7 when read back, the low byte will contain the first eight pixels of the row with data bit 0 corresponding to the left most bit in the pixel row. the high byte will contain the remaining four pixels in the least significant nibble. the remaining 4 bits, shown as ?x?, are ?don?t care? bits, and should be discarded. bit 3 of the high byte corresponds to the right most pixel in the pixel row. this is shown in table 4 . table 4. character rom read data register address d7 d6 d5 d4 d3 d2 d1 d0 font s - 2 color 0x0000?0x2ffe pixel[7:0] +1 xxxx pixel[11:8] font s - 4 color 0x3000?0x3ffe pixel[7:0] +1 xxxx pixel[11:8] font s - 2 color 0x4000?0x6ffe pixel[7:0] +1 xxxx pixel[11:8] font s - 4 color 0x7000?0x7ffe pixel[7:0] +1 xxxx pixel[11:8] display page 0x8000?0x83ff x char_code[7:4] or reserved char_code[3:0] or attr_code display page ram full 512 displayable character access this address range (0x8000?0x81ff) contains the 512 characters, which comprise the displayable osd screens. there must be at least one end-of-screen code (0x00) in this range to prevent unpredictable behavior. note: to avoid any unpredictable behavior, this range should be cleared by writin ga0tobit3ofthe frmctrl1 register, 0x8400, immediately after power up. there may also be one or more pairs of end-of-line and skip line codes. the character code is 9 bits long. the codes and characters are written as 8-bit bytes, but are stored with their attributes in groups of 13 bits. when writing, one byte describes a displayed character (cc), attribute code (ac), end-of-screen (eos), end-of-line (eol) or skip line (sl) code. when reading characters from ram, bit 1 of the character font access register (0x8402) determines whether the lower 8 bits or upper 5 bits of the page ram are returned. table 5 gives the lower byte read, which is the first 8 character code bits when bit 1 of the character font access register is a 0. table 6 gives the upper byte read, which is the 9th character code bit and 4 attribute code bits when this bit is set to a 1. LM1276 www.national.com 26
LM1276 address map (continued) table 5. page ram lower byte read data address range d7 d6 d5 d4 d3 d2 d1 d0 0x8000?0x81ff char_code[7:0] table 6. page ram upper byte read data address d7 d6 d5 d4 d3 d2 d1 d0 0x8000?0x81ff x x x cc[8] attr_code[3:0] ram data format each of the 512 locations in the page ram is comprised of a 13-bit code consisting of an 9-bit character or control code, and a 4-bit attribute code. each of the characters is stored in sequence in the page ram in bits 8:0. special codes are used between lines to show where one line ends and the next begins, and also to allow blank (or ?skipped?) single scan lines to be added between character lines. table 7 shows the format of a character stored in ram. note that even though this is a 13-bit format, reading and writing characters and codes is done in 8-bit bytes. table 7. page ram format (9-bit mode) attribute code character code att[3:0] cc[8:0] bits 8-0 determined which of the 512 characters is to be called from the character rom. bits 12?9 address one of the 16 attributes in the table containing the colors and enhanced features to be used for this particular character. two separate attribute tables are used, one for 2-color characters, and the other for 4-color characters. note there are 16 available attributes for 2-color characters and a different set of 16 available attributes for 4-color characters. end-of-line code to signify the end of a line of characters, a special end-of-line (eol) code is used in place of a character code. this code, shown in table 8 tells the osd generator that the character and attribute codes which follow must be placed on a new line in the displayed window. bits 8?1 are zeros, bit 0 is a one. the attribute that is stored in page ram along with this code is not used. table 8. end-of-line code attribute code end-of-line code att[3:0] 000000001 skip-line code in order to allow finer control of the vertical spacing of character lines, each displayed line of characters may have up to 15 skipped (i.e., blank) lines between it and the line beneath it. each skipped line is treated as a single character pixel line, so multiple scan lines may actually be displayed in order to maintain accurate size relative to the character cell. an internal algorithm maintains vertical height proportionality (see the section on constant character height mechanism). to specify the number of skipped lines, the first character in each new line of characters is interpreted differently than the others in the line. its data are interpreted as shown in table 9 , with the attribute bits setting the color of the skipped lines. table 9. skipped-line code attribute code number of skipped lines att[3:0] xxxxx sl[3:0] bits 8?4 are reserved and should be set to zero. bits 3?0 determine how many blank pixel lines will be inserted between the present line of display characters and the next. a range of 0?15 may be selected. bits 12?9 determine which attribute the pixels in the skipped lines will have, which is always called from the two-color attribute table. the pixels will have the background color (color 0) of the selected attribute table entry. note that the pixels in the first line immediately below the character may be overwritten by the pixel override system that creates the button box. (refer to the button box formation section for more information). after the first line, each new line always starts with an sl code, even if the number of skipped lines to follow is zero. this means an sl code must always follow an eol code. an eol code may follow an sl code if several ?transparent? lines are required between sections of the window. see example 3 in the lm1247 data sheet for a case where skipped lines of zero characters are displayed, resulting in one window being displayed in two segments. end-of-screen code to signify the end of the window, a special end-of-screen (eos) code is used in place of a end-of-line (eol) code. there must be at least one eos code in the page ram to avoid unpredictable behavior. this can be accomplished by clearing the ram by writin ga0tobit3ofthe frmctrl1 register, 0x8400, immediately after power up. LM1276 www.national.com 27
LM1276 address map (continued) table 10. end-of-screen code attribute code end-of-screen code att[3:0] 000000000 bits 8?0 are all zeros. bits 12?9 will have the previously entered ac but this is not used and so these bits are ?don?t cares?. osd control registers these registers, shown in table 11 , control the size, position, enhanced features and rom bank selection of up to two independent osd windows. these registers are compatible to the lm1246 osd control registers. any bits marked as ?x? are reserved and should be written to with zeros and should be ignored when the register is read. additional register detail is provided in the control register definitions section, later in this document. table 11. osd control register detail register address default d7 d6 d5 d4 d3 d2 d1 d0 frmctrl1 0x8400 0x98 aszdn aszen fen td cdpr d2e d1e ose frmctrl2 0x8401 0x80 pixels_per_line[2:0] blink_period[4:0] charfontacc 0x8402 0x00 srst rsv rsv limit vsypol hsypol attr font4 vblankdur 0x8403 0x10 x vblank_duration[6:0] charhtctrl 0x8404 0x51 char_height[7:0] bbhlctrlb0 0x8405 0xff g[1:0] r[2:0] b[2:0] bbhlctrlb1 0x8406 0x01 xxxxxxx g[2] bbllctrlb0 0x8407 0x00 g[1:0] r[2:0] b[2:0] bbllctrlb1 0x8408 0x00 xxxxxxx g[2] chsdwctrlb0 0x8409 0x00 g[1:0] r[2:0] b[2:0] chsdwctrlb1 0x840a 0x00 xxxxxxx g[2] romsigctrl 0x840d 0x00 xxxxxxxcrs romsigdatab0 0x840e 0x00 crc[7:0] romsigdatab1 0x840f 0x00 crc[15:8] hstrt1 0x8410 0x62 hpos1[7:0] vstrt1 0x8411 0x32 vpos1[7:0] w1strtadrl 0x8412 0x00 addr1[7:0] w1strtadrh 0x8413 0x00 xxxxxxx addr1[8] colwidth1b0 0x8414 0x00 col1[7:0] colwidth1b1 0x8415 0x00 col1[15:8] colwidth1b2 0x8416 0x00 col1[23:16] colwidth1b3 0x8417 0x00 col1[31:24] hstrt2 0x8418 0x56 hpos2[7:0] vstrt2 0x8419 0x5b vpos2[7:0] w2strtadrl 0x841a 0x00 addr2[7:0] w2strtadrh 0x841b 0x01 xxxxxxx addr2[8] colwidth2b0 0x841c 0x00 col2[7:0] colwidth2b1 0x841d 0x00 col2[15:8] colwidth2b2 0x841e 0x00 col2[23:16] colwidth2b3 0x841f 0x00 col2[31:24] any registers in the range of 0x8420?0x8426 are for national semiconductor internal use only and should not be written to under application conditions. fade_intvl 0x8429 0x35 v_intvl[3:0] h_invtvl[3:0] preamplifier control these registers, shown in table 12 , control the gains, dac outputs, pll, horizontal and vertical blanking, osd contrast and dc offset of the video outputs. registers 0x8430?0x8437 are compatible to the lm1246 registers. any bits marked as ?x? are reserved and should be written to with zeros and should be ignored when the register is read. additional register detail is provided in the control register definitions section , later in this document. LM1276 www.national.com 28
LM1276 address map (continued) table 12. LM1276 preamplifier interface registers register address default d7 d6 d5 d4 d3 d2 d1 d0 bgainctrl 0x8430 0x60 x bgain[6:0] ggainctrl 0x8431 0x60 x ggain[6:0] rgainctrl 0x8432 0x60 x rgain[6:0] contrctrl 0x8433 0x60 x contrast[6:0] dac1ctrl 0x8434 0x80 dac1[7:0] dac2ctrl 0x8435 0x80 dac2[7:0] dac3ctrl 0x8436 0x80 dac3[7:0] dac4ctrl 0x8437 0x80 dac4[7:0] dacosddcoff 0x8438 0x24 dcf[1:0] osd cont[2:0] dc offset[2:0] globalctrl 0x8439 0x00 bi[7:6] bi_en pllcal rsv rsv ps bv auxctrl1 0x843a 0x03 hb_pos[4:0] hbpos _en rsv hbd auxctrl2 0x843e 0x06 rsv rsv clmp clmp sw oor vb2 rsv rsv osd_transp tone 0x85c0 0x7f rsv osd tone[6:0] emphasis centf 0x85c1 0x80 centf[3:0] rsv ablctrl0 0x85c4 0x0f rsv abl0[3:0] ablctrl1 0x85c5 0x0f rsv abl1[3:0] ablctrl2 0x85c6 0x0f rsv abl2[3:0] ablctrl3 0x85c7 0x0f rsv abl3[3:0] peakcntltxt 0x85c8 0x30 rsv tm_ovrsht[2:0] hlcontrtxt 0x85c9 0x60 rsv hilight_contrast[6:0] peakcntlpic 0x85ca 0x03 rsv pm_ovrsht[2:0] hlcontrpic 0x85cb 0x60 rsv hilight_contrast[6:0] peakcntlmov 0x85cc 0x03 rsv mm_ovrsht[2:0] hlcontrtmov 0x85cd 0x60 rsv hilight_contrast[6:0] two-color attribute ram this ram is identical to that of the lm1247. please refer to the lm1247 datasheet for details. four-color attribute ram this ram is identical to that of the lm1247. please refer to the lm1247 datasheet for details. auto size and hi-brite registers these registers, shown in table 13 provide measured values for the auto size function and control the hi-brite function. registers 0x8580 ? 0x858a are compatible to the lm1246 auto size registers. reserved bits are for internal use and should not be written to, and any value read should be ignored. table 13. LM1276 auto size registers register address default d7 d6 d5 d4 d3 d2 d1 d0 h_fp0 0x8580 0xff hfp[7:0] h_fp1 0x8581 0x07 rsv hfp[10:8] hf_s0 0x8582 0xff hfl_hs[7:0] hf_s1 0x8583 0x03 rsv hfl hs[9:8] h_bp0 0x8584 0xff hbp[7:0] h_bp1 0x8585 0x07 rsv hbp[10:8] v_fp0 0x8586 0xff vfp[7:0] v_fp1 0x8587 0x07 rsv vfp[10:8] v_syn_d 0x8588 0xff vsync[7:0] LM1276 www.national.com 29
LM1276 address map (continued) table 13. LM1276 auto size registers (continued) register address default d7 d6 d5 d4 d3 d2 d1 d0 v_bp0 0x8589 0xff vbp[7:0] v_bp1 0x858a 0x07 rsv vbp[10:8] v_fp0_prv 0x858b 0xff vfp prev [7:0] v_fp1_prv 0x858c 0x07 vfp prev[10:8] v_syn_prv 0x858d 0xff vsync prev [7:0] v_bp0_prv 0x858e 0xff vbp prev [7:0] v_bp1_prv 0x858f 0x07 vbp prev[10:8] hb control 0x8590 0x40 intr_en limit whldis fshen rsv rsv rsv rsv status 0x8591 0x00 intr rsv rsv rsv rsv rsv rsv rsv mcu command 0x8592 0xff mcu command[7:0] sub command 0x8593 0xff sub command[7:0] seq num 0x859a 0xff seq num[7:0] pll lock 0xfff8 0x00 rsv rsv lock set lock orr rsv rsv rsv rsv h input sel 0xfffd 0x01 rsv rsv rsv rsv hsel rsv rsv rsv building display pages the osd window the display page ram contains all of the 9-bit display character codes and their associated 4-bit attribute codes, and the special 13-bit page control codes ? the end-of-line, skip-line parameters and end-of-screen characters. the LM1276 has a distinct advantage over many osd generators in that it allows variable size and format windows. the window size is not dictated by a fixed geometric area of ram. instead, 512 locations of 13-bit words are allocated in ram for the definition of the windows, with special control codes to define the window size and shape. window width can be any length supported by the number of pixels per line that is selected divided by the number of pixels in a character line. it must be remembered that osd characters displayed during the monitor blanking time will not be displayed on the screen, so the practical limit to the number of horizontal characters on a line is reduced by the number of characters within the horizontal blanking period. the eos code tells the osd generator that the character codes following belong to another displayed window at the next window location. an eos code may follow normal characters or an sl code, but never an eol control code, because eol is always followed by an ac plus an sl code. writing to the page ram the display page ram can contain up to 512 of the above listed characters and control codes. each character, or control code will consume one of the possible 512 locations. for convenience, writin ga1tobit3ofthe frame control register (0x8400) resets all page ram values to zero. this should be done at power up to avoid unpredictable behavior. display window 1 will also start at the first location (corresponding to the i 2 c address 0x8000). this location must always contain the skip-line (sl) code associated with the first line of display window 1. the attribute for this sl code must be written before the sl code itself, and will be stored in the lower four bits of this memory location. subsequent locations should contain the characters to be displayed on line 1 of display window 1, until the eol code or eos code is written into the display page-ram. the skip-line parameters associated with the next line must always be written to the location immediately after the preceding line?s end-of-line character. the only exception to this rule is when an end-of-screen character (value 0x0000) is encountered. it is important to note that an end-of-line character should not precede an end-of-screen character (otherwise the end-of-screen character will be interpreted as the next line?s skip-line code). instead, the end-of-screen code will end the line and also end the window, making it unnecessary to precede it with an eol. the i 2 c format for writing a sequence of display characters is minimized by allowing sequential characters with the same attribute code to send in a string as follows: byte #1: i 2 c slave address byte #2: lsb register address byte #3: msb register address byte #4: attribute table entry to use for the following s skip-line code or characters byte #5: first display character, sl parameter, eol or eos control code byte #6: second display character, sl parameter, eol or eos control code byte #7: third display character, sl parameter, eol or eos control code byte #n: last display character in this color sequence, sl parameter, eol or eos control code to use the associated attribute table entry. LM1276 www.national.com 30
building display pages (continued) this communication protocol is known as the auto attribute mode, which is also used by the lm1237 and lm1247. please see examples of usage for this mode in the lm1247 datasheet. table 14. sequence of transmitted bytes enhanced page ram address modes since the LM1276 is able to support 9-bit character codes, usually two bytes of page ram information has to be sent to every location. to avoid this, the LM1276 addressing control system has 3 additional addressing modes offering increased flexibility that may be helpful in sending data to the page ram. some of the left over bits in the attribute byte are employed as data control bits to select the desired addressing mode as shown in table 6 . this is identified as the first byte sent in a write operation or the page ram?s upper byte read in table 7. table 15. attribute byte attribute byte x dc[1] dc[0] cc[8] att[3:0] auto attribute mode the auto attribute mode is the standard lm1247 mode that is described above in the writing to the page ram section. the attribute byte is shown in table 16 . table 16. auto attribute mode attribute byte x 0 0 0 att[3:0] when bits 6?5 are 0, the 9th character code and the 4-bit attribute code will be automatically applied to all the character codes transmitted after this attribute byte, as in the lm1237 and lm1247. this mode is useful for sending character codes that use the same attribute, and which are in the same 4 out of 8 banks of the page rom. a new transmission must be started to access another character that is not in the same 4 banks of the page rom, and no further attribute codes can follow without stopping and restarting a new transmission. the page ram address is automatically incremented starting with the initial lsb and msb address in the beginning of the sequence. two byte communication mode the two byte communication mode allows different attribute and character codes to be sent within one transmission without stopping. the entire 512-character page rom is also fully accessible in this mode, without the need to stop and restart transmission. the attribute byte is shown in table 17 , and the sequence of transmitted bytes is shown in table 18 . either another attribute & character code pair or a stop must follow after each character code. the page ram address is automatically incremented just as in the auto attribute mode above. table 17. two byte communication mode attribute byte x 0 1 cc[8] att[3:0] table 18. sequence of transmitted bytes half random address mode the half random address mode allows different attribute and character codes to be sent within one transmission in the same way as the two byte communication mode. the entire 512-character page rom is fully accessible in this mode, without the need to stop and restart transmission. the advantage of half random addressing over the two byte mode is that the page ram addresses do not have to be written to in a sequential order. however, the page ram addresses cannot be entirely random, as they must be within one half of the page ram. a new transmission must be restarted to switch to another half of the page ram. LM1276 www.national.com 31
building display pages (continued) the page ram address is not automatically incremented in this mode. this mode is very useful for modifying character codes and attributes in the first 256 locations of the page ram. the attribute byte is shown in table 19 , and the sequence of transmitted bytes is shown in table 20 . either another lsb address & attribute & character code or a stop must follow after each character code. table 19. half random address mode attribute byte x 1 0 cc[8] att[3:0] table 20. sequence of transmitted bytes full random address mode the full random address mode is very similar to the half random address mode. however, the advantage is that the page ram addresses can now be entirely random. there is no longer a restriction to only one half of the page ram. the page ram address is not automatically incremented in this mode. this is very useful for modifying character codes and attributes anywhere in the page ram without starting a new transmission sequence. the full random address mode is the most flexible mode of transmission. the attribute byte is shown in table 21 , and the sequence of transmitted bytes is shown in table 22 . either another lsb address & msb address & attribute & character code or a stop must follow after each character code. table 21. full random address mode attribute byte x 1 1 cc[8] att[3:0] table 22. sequence of transmitted bytes control register definitions osd interface registers frame control register 1: frmctrl1 (0x8400) autosize done autosize fade i/o trans clear win2 win1 osd aszdn aszen fen td cdpr d2e d1e ose bit 0 on-screen display enable. the on-screen display will be disabled when this bit is a zero. when this bit is a one the on-screen display will be enabled. this controls both window 1 and window 2. bit 1 display window 1 enable. when this bit and bit 0 of this register are both ones, display window 1 is enabled. if either bit is a zero, then display window 1 will be disabled. bit 2 display window 2 enable. when this bit and bit 0 of this register are both ones, display window 2 is enabled. if either bit is a zero, then display window 2 will be disabled. bit 3 clear display page ram. writing a one to this bit will result in setting all of the display page ram values to zero. this bit is automatically cleared after the operation is complete. this bit is initially asserted by default at power up, and will clear itself back to zero shortly after. thus, the default value is one only momentarily, and then will remain zero until manually asserted again or until the power is cycled. bit 4 transparent disable. when this bit is a zero, a palette color of black (i.e., color palette look-up table value of 0x00) in the first 8 palette look-up table address locations (i.e., att0?att7) will be interpreted as transparent. when this bit is a one, the color will be interpreted as black. LM1276 www.national.com 32
control register definitions (continued) bit 5 fade in/out enable. when this bit is a 1, the osd fade in/fade out function is enabled. when this bit is a 0, the function is disabled. bit 6 auto size enable. when this bit is a 1, the auto size function is enabled. once video detection and measurement is completed, the bit will automatically clear itself back to 0. bit 7 auto size done. when the device has completed auto size calculations, this bit will automatically be set high by the chip to indicate to the mcu that the auto size data registers are valid and available. this bit is automatically cleared when the mcu sets the aszen bit (0x8400[6]), or when the device programs a calibration sequence for the windows hibrite software. frame control register 2: frmctrl2 (0x8401) pixels per line blink period pl[2:0] bp[4:0] bits 4?0 blink period. these five bits set the blink period of the blinking feature, which is determined by mulitiplying the value of these bits by 8, and then multiplying the result by the vertical field rate. bits 7?5 pixels per line. these three bits determine the number of pixels per line of osd characters . see table 23 , which gives the maximum horizontal scan rate. also see table 2 . table 23. osd pixels per line bits 7?5 description max horizontal frequency (khz) 0x0 704 pixels per line 110 0x1 768 pixels per line 110 0x2 832 pixels per line 110 0x3 896 pixels per line 110 0x4 960 pixels per line 110 0x5 1024 pixels per line 108 0x6 1088 pixels per line 102 0x7 1152 pixels per line 96 character font access register: charfontacc (0x8402) reset reserved reserved vdi v sync h sync select plane srst rsv rsv limit vsypol hsypol attr font4 bit 0 this is the color bit plane selector. this bit must be set to 0 to read or write a two-color attribute from the range 0x0000 to 0x2fff. when reading or writing four-color attributes from the range 0x3000 to 0x3fff, this bit is set to 0 for the least significant plane and to 1 for the most significant plane. it is also required to set this bit to read the individual bit planes of the four color character fonts in 0x3000 to 0x3fff and 0x7000 to 0x7fff. bit 1 this is the character/attribute selector. this applies to reads from the display page ram (address range 0x8000?0x81ff). when a 0, the character code is returned and when a 1, the attribute code is returned. bit 2 this selects the v input polarity. if bit = 0, a positive h sync input signal is required. (default) if bit = 1, a negative h sync input signal is required. bit 3 this selects the v sync input polarity. if bit = 0, a positive v sync input signal is required. (default) if bit = 1, a negative v sync input signal is required. bit 4 this bit limits the period during which video data may be detected. if the bit is set to 1 then the valid data active period is limited to the vertical blanking time, as set by the vertical blanking register. if a string of 80 clock pulses is received during this time it is accepted as valid. if a string of 80 pulses is not received until during the active video time, then this data is ignored. if the bit is set to ?0? (default), then the first 80 pulse clock string that is detected is considered to be valid, even if this is during the active video time. LM1276 www.national.com 33
control register definitions (continued) bit 5 reserved. this bit should be set to zero. bit 6 reserved. this bit should be set to zero. bit 7 setting this bit will cause a software reset. all registers (except this one) are loaded with their default values. all operations currently in progress are aborted (except for i 2 c transactions). this bit automatically clears itself when the reset has been completed. vertical blank duration register: vblankdur (0x8403) reserved vertical blanking duration rsv vb[6:0] bits 6?0 this register determines the duration of the vertical blanking signal in scan lines. when vertical blanking is enabled, it is recommended that this register be set to a number greater than 0x0a. bit 7 reserved. this bit should be set to zero. osd character height register: charhtctrl (0x8404) ch[7:0] bits 7?0 this register determines the osd character height as described in the section constant character height mechanism. the values of this register is equal to the approximate number of osd height compensated lines required on the screen, divided by 4. this value is not exact due to the approximation used in scaling the character. example: if approximately 384 osd lines are required on the screen (regardless of the number of scan lines) then the character height control register is programmed with 81 (0x51). enhanced feature register 1: button box highlight color bbhlctrlb1 (0x8406) bbhlctrlb0 (0x8405) reserved highlight - green highlight - red highlight - blue xxxxxxx g[2:0] r[2:0] b[2:0] bits 8?0 these determine the button box highlight color. bits 15?9 reserved. these bits should be set to zero. enhanced feature register 2: button box lowlight color bbllctrlb1 (0x8408) bbllctrlb0 (0x8407) reserved lowlight - green lowlight - red lowlight - blue xxxxxxx g[2:0] r[2:0] b[2:0] bits 8?0 these determine the button box lowlight color. bits 15?9 reserved. these bits should be set to zero. enhanced feature register 3: heavy button box lowlight/shading/shadow chsdwctrlb1 (0x840a) chsdwctrlb0 (0x8409) reserved shadow - green shadow - red shadow - blue xxxxxxx g[2:0] r[2:0] b[2:0] bits 8?0 these registers determine the heavy button box lowlight, shading or shadow color. bits 15?9 reserved. these bits should be set to zero. LM1276 www.national.com 34
control register definitions (continued) rom signature control register: romsigctrl (0x840d) reserved check xxxxxxxcrs bit 0 this controls the calculation of the rom signature. setting this bit causes the rom to be read sequentially and a 16-bit checksum calculated over the 256 characters. the sum, modulo 65535, is stored in the rom signature data register, and this bit is then automatically cleared. bits 7?1 reserved. these should be set to zero. rom signature data: romsigdatab1 (0x840f) romsigdatab0 (0x840e) 16-bit checksum crc[15:0] bits 15?0 this is the checksum of the 256 rom characters truncated to 16 bits (modulo 65535). all devices with the same masked rom will have the same checksum. display window 1 horizontal start address: hstrt1 (0x8410) window 1 horizontal start location hpos1[7:0] bits 7?0 there are two possible osd windows which can be displayed simultaneously or individually. this register determines the horizontal start position of window 1 in osd pixels (not video signal pixels). the actual position, to the right of the horizontal flyback pulse, is determined by multiplying this register value by 4 and adding 30. due to pipeline delays, the first usable start location is approximately 42 osd pixels following the horizontal flyback time. for this reason, we recommend this register be programmed with a number larger than 2, otherwise improper operation may result. display window 1 vertical start address: vstrt1 (0x8411) window 1 vertical start address vpos1[7:0] bits 7?0 this register determines the vertical start position of the window 1 in constant-height character lines (not video scan lines). the actual position is determined by multiplying this register value by 2. (note: each character line is treated as a single auto-height character pixel line, so multiple scan lines may actually be displayed in order to maintain accurate position relative to the osd character cell size. (see the constant character height mechanism section.) this register should be set so the entire osd window is within the active video. display window 1 start address: w1strtadrh (0x8413) w1strtadrl (0x8412) reserved window 1 start address xxxxxxx addr1[8:0] bits 8?0 this register determines the starting address of display window 1 in the display page ram. the power-on default of 0x00 starts window 1 at the beginning of the page ram (0x8000). this first address location always contains the sl code for the first line of display window 1. this register is new for the LM1276 and allows window 1 to start anywhere in the page ram rather than just at 0x8000. note that the address this points to in page ram must always contain the sl code for the first line of the window. bits 15?9 these bits are reserved and should be set to zero. LM1276 www.national.com 35
control register definitions (continued) display window 1 column width: colwidth1b3 (0x8417) colwidth1b2 (0x8416) window 1 column width - high bytes col1[31:16] colwidth1b1 (0x8415) colwidth1b0 (0x8414) window 1 column width - low bytes col1[15:0] bits 31?0 these are the display window 1 column width 2x enable bits. these 32 bits correspond to columns 31?0 of display window 1, respectively. a value of zero indicates the column will have normal width (12 pixels). a ?1? indicates the column will be twice as wide as normal (24 pixels). for the double wide case, each character font pixel location will be displayed twice, in two consecutive horizontal pixel locations. the user should note that if more than 32 display characters are programmed to reside on a line, then all display characters after the first thirty-two will have normal width (12 pixels). display window 2 horizontal start address: hstrt2 (0x8418) window 2 horizontal start address hpos2[7:0] bits 7?0 this register determines the horizontal start position of window 2 in osd pixels (not video signal pixels). the actual position, to the right of the horizontal flyback pulse, is determined by multiplying this register value by 4 and adding 30. due to pipeline delays, the first usable start location is approximately 42 osd pixels following the horizontal flyback time. for this reason, we recommend this register be programmed with a number larger than 2, otherwise improper operation may result. display window 2 vertical start address: vstrt2 (0x8419) window 2 vertical start address vpos2[7:0] bits 7?0 this register determines the vertical start position of window 2 in constant-height character lines (not video scan lines). the actual position is determined by multiplying this register value by 2. (note: each character line is treated as a single auto-height character pixel line, so multiple scan lines may actually be displayed in order to maintain accurate position relative to the osd character cell size. (see the constant character height mechanism section.) this register should be set so the entire osd window is within the active video. display window 2 start address: w2strtadrh (0x841b) w2strtadrl (0x841a) reserved window 2 start address xxxxxxx addr2[8:0] bits 8?0 this register determines the starting address of display window 2 in the display page ram. the power-on default of 0x10 starts window 2 at the midpoint of the page ram (0x8100). this location always contains the sl code for the first line of display window 2. bits 15?9 these bits are reserved and should be set to zero. display window 2 column width: colwidth2b3 (0x841f) colwidth2b2 (0x841e) window 2 column width - high bytes col2[31:16] LM1276 www.national.com 36
control register definitions (continued) colwidth2b1 (0x841d) colwidth2b0 (0x841c) window 2 column width - low bytes col2[15:0] bits 31?0 these are the display window 2 column width 2x enable bits. these thirty-two bits correspond to columns 31?0 of display window 2, respectively. a value of zero indicates the column will have normal width (12 osd pixels). a value of one indicates the column will be twice as wide as normal (24 osd pixels). for the double wide case, each character font pixel location will be displayed twice, in two consecutive horizontal pixel locations. the user should note that if more than 32 display characters are programmed to reside on a line, then all display characters after the first thirty-two will have normal width (12 pixels). fade in/fade out interval register: fade_intvl (0x8429) vertical interval horizontal interval v_intvl[3:0] h_intvl[3:0] bits 7?4 these three bits determine the interval for fading in or fading out the osd window in the vertical direction. bits 3?0 these three bits determine the interval for fading in or fading out the osd window in the horizontal direction. pre-amplifier interface registers blue channel gain: bgainctrl (0x8430) res?d blue gain rsv bgain[6:0] bits 6?0 this register determines the gain of the blue video channel. this affects only the blue channel whereas the contrast register (0x8433) affects all channels. bit 7 reserved and should be set to zero. green channel gain: ggainctrl (0x8431) res?d green gain rsv ggain[6:0] bits 6?0 this register determines the gain of the green video channel. this affects only the green channel whereas the contrast register (0x8433) affects all channels. bit 7 reserved and should be set to zero. red channel gain: rgainctrl (0x8432) res?d red gain rsv rgain[6:0] bits 6?0 this register determines the gain of the red video channel. this affects only the red channel whereas the contrast register (0x8433) affects all channels. bit 7 reserved and should be set to zero. contrast control: contrctrl (0x8433) res?d contrast rsv contrast[6:0] LM1276 www.national.com 37
pre-amplifier interface registers (continued) bits 6?0 this register determines the contrast gain and affects all three channels, blue, red and green. bit 7 reserved and should be set to zero. dac 1 output level: dac1ctrl (0x8434) dac 1 output level dac1[7:0] bits 7?0 this register determines the output of dac 1. the full-scale output is determined by bit 6 of the dac config, osd contrast & dc offset register (0x8438). dac 2 output level: dac2ctrl (0x8435) dac 2 output level dac2[7:0] bits 7?0 this register determines the output of dac 2. the full-scale output is determined by bit 6 of the dac config, osd contrast & dc offset register (0x8438). dac 3 output level: dac3ctrl (0x8436) dac 3 output level dac3[7:0] bits 7?0 this register determines the output of dac 3. the full-scale output is determined by bit 6 of the dac config, osd contrast & dc offset register (0x8438). dac 4 output level: dac4ctrl (0x8437) dac 4 output level dac4[7:0] bits 7?0 this register determines the output of dac 4. the output of this dac can be scaled and mixed with the outputs of dacs 1?3 as determined by bit 7 of the dac config, osd contrast & dc offset register (0x8438). dac config, osd contrast & dc offset: dacosddcoff (0x8438) dac options osd contrast dc offset dcf[1:0] osd[2:0] dc[2:0] bits 2?0 these determine the dc offset of the three video outputs, blue, red and green. bits 5?3 these determine the contrast of the internally generated osd. bit 6 when this bit is a 0, the full-scale outputs of dacs 1?3 are 0.5v to 4.5v. when it is a 1, the full-scale range is 0.5v to 2.5v. bit 7 when this bit is a 0, the dac 4 output is independent. when it is a 1, the dac 4 output is scaled by 50% and added to the outputs of dacs 1?3. global video control: globalctrl (0x8439) burn in contrast burn in pll res?d res?d power blank bi[1:0] bi_en pllcal rsv rsv ps bv LM1276 www.national.com 38
pre-amplifier interface registers (continued) bit 0 when this bit is a 1, the video outputs are blanked (set to black level). when it is a 0, video is not blanked. bit 1 when this bit is a 1, the analog sections of the preamplifier are shut down for low power consumption. when it is a 0, the analog sections are enabled. bits 3?2 reserved. bit 4 when this bit is set high, the calibration sequence for the pll auto mode is initiated, the pll auto mode is activated, and will unset itself upon completion. bit 5 this bit will enable the burn in screen. bits 7?6 these bits determine the contrast level of the burn in screen. auxiliary control 1: auxctrl1 (0x843a) horizontal blank position h. blank reserved h blnk hbpos[4:0] hbpos_en rsv hbd bit 0 when this bit is a 0, the horizontal blanking input at pin 28 is gated to the video outputs to provide horizontal blanking. when it is a 1, the horizontal blanking at the outputs is disabled. bit 1 reserved. bit 2 when this bit is a 1, the position of the horizontal blanking pulse can be programmably varied relative to the horizontal flyback in number of pixels. when this bit is a 0, which is by default, the horizontal blanking pulse position will not be programmable. bits 7?3 these 5 bits determine the position of the horizontal blanking pulse with respect to the horizontal flyback in number of pixels. auxiliary control 2: auxctrl2 (0x843e) res?d res?d clamp clamp switch osd vblank res?d res?d rsv rsv clmp clmp sw oor vbl rsv rsv bits 1?0 reserved and should be set to zero. bit 2 this is the vertical blanking register. when this bit is a 1, vertical blanking is gated to the video outputs. when set to a 0, the video outputs do not have vertical blanking. bit 3 this is the osd override bit. this should be set to 0 for normal operation. when set to a 1, the video outputs are disconnected and osd only is displayed. this is useful for the osd display of special conditions such as ?no signal? and ?input signal out of range?, to avoid seeing unsynchronized video. bit 4 setting this bit will internally tie the clamp pin to the horizontal sync pin, and the clamp pin will not require an external input signal. bit 5 this is the clamp polarity bit. when set to a 0, the LM1276 expects a positive going clamp pulse. when set to a 1, the expected pulse is negative going. bits 7?6 reserved and should be set to zero. osd tone transparency: osd transp tone (0x85c0) res?d osd tone rsv osdtone[6:0] bits 6?0 these bits determine the transparency level of the osd background. bit 7 reserved and should be set to zero. LM1276 www.national.com 39
pre-amplifier interface registers (continued) center frequency: emphasis_centf(0x85c1) center frequency res?d res?d res?d res?d centf[3:0] rsv rsv rsv rsv bits 3?0 reserved and should be set to zero. bits 7?4 these 4 bits control the center frequency adjustment of the hi-brite window video signal for enhancement. abl control 0 ablctrl0 (0x85c4) reserved abl current rsv abl0[3:0] bits 3?0 these bits determine the abl current limiting threshold for abl setting 0. bits 7?4 reserved and should be set to zero. abl control 1 ablctrl1 (0x85c5) reserved abl current rsv abl1[3:0] bits 3?0 these bits determine the abl current limiting threshold for abl setting 1. bits 7?4 reserved and should be set to zero. abl control 2 ablctrl2 (0x85c6) reserved abl current rsv abl2[3:0] bits 3?0 these bits determine the abl current limiting threshold for abl setting 2. bits 7?4 reserved and should be set to zero. abl control 3 ablctrl3 (0x85c7) reserved abl current rsv abl3[3:0] bits 3?0 these bits determine the abl current limiting threshold for abl setting 3. bits 7?4 reserved and should be set to zero. peak control text peakcntltxt (0x85c8) reserved rsv text mode overshoot rsv rsv tm_ovrsht[2:0] bits 2?0 these bits determine the amount of overshoot for the text mode bits 7?3 reserved and should be set to zero. LM1276 www.national.com 40
pre-amplifier interface registers (continued) highlight contrast text: hlcontrtxt (0x85c9) res?d hilight_contrast rsv hilight_contrast[6:0] bits 6?0 these bits determine the amount of highlight contrast for the text mode. bit 7 reserved and should be set to zero. peak control pic peakcntlpic (0x85ca) reserved pic mode overshoot rsv pm_ovrsht[2:0] bits 2?0 these bits determine the amount of overshoot for the pic mode bits 7?3 reserved and should be set to zero. highlight contrast pic: hlcontrpic (0x85cb) res?d hilight_contrast rsv hilight_contrast[6:0] bits 6?0 these bits determine the amount of highlight contrast for the pic mode. bit 7 reserved and should be set to zero. peak control movie peakcntlmov (0x85cc) reserved text mode overshoot rsv mm_ovrsht[2:0] bits 2?0 these bits determine the amount of overshoot for the movie mode bits 7?3 reserved and should be set to zero. highlight contrast movie: hlcontrtxt (0x85cd) res?d hilight_contrast rsv hilight_contrast[6:0] bits 6?0 these bits determine the amount of highlight contrast for the movie mode. bit 7 reserved and should be set to zero. auto size registers horizontal front porch duration: h_fp1 (0x8581) h_fp0 (0x8580) reserved horizontal front porch duration rsv rsv rsv rsv rsv hfp[10:0] bits 10?0 this is an 11-bit wide register that records the lowest measured value of the horizontal front porch during video detect. when no video is detected, this register should return a value of zero. once measurement is completed and the auto size enable bit has cleared itself back to 0, the measured data is ready to be read by the microcontroller. reading this register before that may give erroneous results. this register resets to default values, ready to record new measured values when the auto size enable bit is set again. LM1276 www.national.com 41
auto size registers (continued) horizontal flyback or sync duration: hf_s1 (0x8583) hf_s0 (0x8582) reserved horizontal flyback or sync duration rsv rsv rsv rsv rsv rsv hfl_hs[9:0] bits 9?0 this is a 10-bit wide register that records the measured value of the horizontal flyback or sync during video detect. when no video is detected, this register should return a value of zero. once measurement is completed and the auto size enable bit has cleared itself back to 0, the measured data is ready to be read by the microcontroller. reading this register before that may give erroneous results. this register resets to default values, ready to record new measured values when the auto size enable bit is set again. horizontal back porch duration: h_bp1 (0x8585) h_bp0 (0x8584) reserved horizontal back porch duration rsv rsv rsv rsv rsv hbp[10:0] bits 10?0 this is an 11-bit wide register that records the lowest measured value of the horizontal back porch during video detect. when no video is detected, the sum of this register and the horizontal flyback or sync should be within 1 pixel of the total number of pixels per line. once measurement is completed and the auto size enable bit has cleared itself back to 0, the measured data is ready to be read by the microcontroller. reading this register before that may give erroneous results. this register resets to default values, ready to record new measured values when the auto size enable bit is set again. vertical front porch duration: v_fp1 (0x8587) v_fp0 (0x8586) reserved vertical front porch duration rsv rsv rsv rsv rsv vfp[10:0] bits 10?0 this is an 11-bit wide register that records the lowest measured value of the vertical front porch in terms of horizontal line periods during video detect. when no video is detected, this register should return a value of zero. once measurement is completed and the auto size enable bit has cleared itself back to 0, the measured data is ready to be read by the microcontroller. reading this register before that may give erroneous results. this register resets to default values, ready to record new measured values when the auto size enable bit is set again. vertical sync duration: v_syn_d (0x8588) vertical flyback or sync duration vsync[7:0] bits 7?0 this is an 8-bit wide register that records the measured value of the vertical flyback or sync in terms of horizontal line periods during video detect. once measurement is completed and the auto size enable bit has cleared itself back to 0, the measured data is ready to be read by the microcontroller. reading this register before that may give erroneous results. this register resets to default values, ready to record new measured values when the auto size enable bit is set again. vertical back porch duration: v_bp1 (0x858a) v_bp0 (0x8589) reserved vertical back porch duration rsv rsv rsv rsv rsv vbp[10:0] LM1276 www.national.com 42
auto size registers (continued) bits 10?0 this is an 11-bit wide register that records the lowest measured value of the vertical back porch in terms of horizontal line periods during video detect. when no video is detected, the sum of this register and the vertical flyback or sync should be within 1 line of the total number of lines per field. once measurement is completed and the auto size enable bit has cleared itself back to 0, the measured data is ready to be read by the microcontroller. reading this register before that may give erroneous results. this register resets to default values, ready to record new measured values when the auto size enable bit is set again. previous field vertical front porch duration: prev_v_bp1 (0x858c) prev_v_bp0 (0x858b) reserved previous vertical front porch duration rsv rsv rsv rsv rsv vfp prev[10:0] bits 10?0 this is an 11-bit wide register that retains the previous lowest measured value of the vertical front porch during video detect in horizontal line periods from the previous field. it is used when interlace mode is present, in order to accurately determine the correct parameter value for the frame. when no video is detected, this register should return a value of zero. reading this register within less than one complete field period after the video detect reset may give erroneous results. this register resets to zero after the video detect reset has been written. previous field vertical sync duration: v_syn_prev (0x858d) previous vertical sync duration vsync prev[7:0] bits 7?0 this is an 8-bit wide register that records the previous measured value of the vertical sync during video detect in horizontal line periods from the previous field. it is used when interlace mode is present, in order to accurately determine the correct parameter value for the frame. reading this register within less than one complete field period after the video detect reset may give erroneous results. this register resets to zero after the video detect reset has been written. previous vertical back porch duration: prev_v_bp1 (0x858f) prev_v_bp0 (0x858e) reserved previous vertical back porch duration rsv rsv rsv rsv rsv vbp prev[10:0] bits 10?0 this is an 11-bit wide register that records the previous lowest measured value of the vertical back porch during video detect in horizontal line periods from the previous field. it is used when interlace mode is present, in order to accurately determine the correct parameter value for the frame. when no video is detected, this sum of this register and the vsync should be with 1 line of the total number of lines per field. reading this register within less than one complete field period after the video detect reset may give erroneous results. this register resets to zero after the video detect reset has been written. hibrite control register: hb control (0x8590) intr_en limit whdis fshen rsv rsv rsv rsv bits 3?0 reserved and should be set to zero. bit 4 this bit must be low for the device to display hibrite software driven windows. this bit must be set high for full screen hibrite by the mcu. bits 4 and 5 must be both high for full screen hibrite. bit 5 this bit when set high will enable the full screen hi-brite feature. this bit can be used by the mcu to highlight the entire screen without the use of the hibrite software. bit 6 this bit must be set to 1 at all times for proper color bar communication. LM1276 www.national.com 43
auto size registers (continued) bits 7 interrupt enable. this bit must be set to 1 to activate the use of the interrupt bit in 0x8591 hibrite status register: status (0x8591) intr rsv rsv rsv rsv rsv rsv rsv bits 6?0 reserved and should be set to zero. bits 7 this bit is the interrupt bit and must be frequently polled (at least 480ms interval) by the mcu for a value of 1, and must be also reset by the mcu thereafter. the interrupt bit will automatically be set high when the software has attempted to send a command to the mcu, with the chip as the messenger. it must be set back to 0 by the mcu afterwards so that it can be set high the next time the mcu software makes another attempt to send a command. mcu command register: mcu command (0x8592) mcu command[7:0] bits 7?0 command. these bits are the mcu command bits. the mcu must read a value of 0x80 from this register. sub command register: sub command (0x8593) sub command[7:0] bits 7?0 sub command. these bits are the sub command bits. if a value of this register is 0x01: this value corresponds to a hibrite software "up" command. 0x02: this value corresponds to a hibrite software "down" command. 0x01: this value corresponds to a prompt for the mcu to perform a "v blank duration adjustment." sequence number: seq num (0x859a) seq num[7:0] bits 7?0 sequence. these bits are the sequence number command bits. the mcu should read this register and take note of the sequence number to compare with the current sequence number. since an mcu sub command is continuously transmitted by the software for a duration of time, the interrupt bit will be set back to high again redundantly, which will falsely notify the mcu of another sub command. to prevent this, the sequence number which is only updated on truly new commands, will prevent redundant commands and have the the mcu set the interrupt but low accordingly. please see the "mcu programmer?s guide" applications note on more detailed information regarding the use of registers 0x8590 - 0x859a. internal pll lock detect control register: status (0xfff8) rsv rsv lock set lock orr rsv rsv rsv rsv bits 3?0 reserved and should be set to zero. bits 5-4 when enabling the osd display, these 2 bits must be enabled first, and then disabled when the osd display is disabled. this should also be done before performing an auto size calculation. bits 7-6 reserved and should be set to zero. h input sel (0xfffd) rsv rsv rsv rsv hsel rsv rsv rsv LM1276 www.national.com 44
auto size registers (continued) bits 2?0 reserved and should be set to zero. bit 3 when enabling this bit, the h flyback input is internally received from the h sync input. bits 7-4 reserved and should be set to zero. attribute table and enhanced features each display character and sl in the display page ram will have a 4-bit attribute table entry associated with it. the user should note that two-color display characters and four-color display characters use two different attribute tables, effectively providing 16 attributes for two-color display characters and 16 attributes for four-color display characters. for two-color characters, the attribute contains the code for the 9-bit foreground color (color 1), the code for the 9-bit background color (color 0), and the character?s enhanced features (button box, blinking, heavy box, shadowing, bordering, etc.). for four-color characters, the attribute contains the code for the 9-bit color 0, the code for the 9-bit color 1, the code for the 9-bit color 2, the code for the 9-bit color 3, and the character?s enhanced features (button box, blinking, heavy box, shadowing, bordering, etc.). two color attribute format the address range for an attribute number, 0 n 15, is provided in table 25 . att2c3n (0x8443+n*4) att2c2n (0x8442+n*4) reserved enhanced feature color 1 - xxxxxxxxxx efb[3:0] c1b[2:1] att2c1n (0x8441+n*4) att2c0n (0x8440+n*4) blue colo r 1 - green colo r 1 - red colo r 0 - blue colo r 0 - green colo r0-red c2b0 c1g[2:0] c1r[2:0] c0b[2:0] c0g[2:0] c0r[2:0] bits 8?0 these nine bits determine the background color (color1), which is displayed when the corresponding osd pixel is a 0. bits 17?9 these nine bits determine the foreground color (color2), which is displayed when the corresponding osd pixel is a 1. bits 21?18 these are the enhanced feature (ef) bits, which determine which feature is applied to the displayed character. the features and their corresponding codes are shown in table 24 . bits 31?22 reserved and should be set to zero. table 24. enhanced feature descriptions bits 21?18 feature description 0000b normal display 0001b blinking 0010b shadowing 0011b bordering 0100b reserved 0101b reserved 0110b reserved 0111b reserved 1000b raised box 1001b blinking and raised box 1010b depressed box 1011b blinking and depressed box 1100b heavy raised box 1101b blinking and heavy raised box 1110b heavy depressed box 1111b blinking and heavy depressed box four color attribute format the address range for an attribute number, 0 n 15, is provided in table 25 . LM1276 www.national.com 45
attribute table and enhanced features (continued) att4c7n (0x8507+n*4) att4c6n (0x8506+n*4) reserved color 3 - xxxxxxxxxxxxxx c3b[2:1] att4c5n (0x8505+n*4) att4c4n (0x8504+n*4) blue colo r 3 - green colo r 3 - red colo r 2 - blue colo r 2 - green colo r2-red c3b0 c3g[2:0] c3r[2:0] c2b[2:0] c2g[2:0] c2r[2:0] att4c3n (0x8503+n*4) att4c2n (0x8502+n*4) reserved enhanced features color 1 - xxxxxxxxxx efb[3:0] c1b[2:1] att4c1n (0x8501+n*4) att4c0n (0x8500+n*4) blue colo r 1 - green colo r 1 - red colo r 0 - blue colo r 0 - green colo r0-red c1b0 c1g[2:0] c1r[2:0] c0b[2:0] c0g[2:0] c0r[2:0] bits 8?0 these nine bits determine color 0 which is displayed when the corresponding osd pixel code is 00b. bits 17?9 these nine bits determine color 1 which is displayed when the corresponding osd pixel code is 01b. bits 21?18 these are the enhanced feature (ef) bits, which determine which feature is applied to the displayed character. the features and their corresponding codes are shown in table 24 . bits 31?22 reserved and should be set to zero. bits 40?32 these nine bits determine color2, which is displayed when the corresponding osd pixel code is 10b. bits 49?41 these nine bits determine color3, which is displayed when the corresponding osd pixel code is 11b. bits 63?50 reserved and should be set to zero. table 25. attribute tables and corresponding addresses attribute number, n two-color attribute table address four-color attribute table address 0000b 0x8440?0x8443 0x8500?0x8507 0001b 0x8444?0x8447 0x8508?0x850f 0010b 0x8448?0x844b 0x8510?0x8517 0011b 0x844c?0x844f 0x8518?0x851f 0100b 0x8450?0x8453 0x8520?0x8527 0101b 0x8454?0x8457 0x8528?0x852f 0110b 0x8458?0x845b 0x8530?0x8537 0111b 0x845c?0x845f 0x8538?0x853f 1000b 0x8460?0x8463 0x8540?0x8547 1001b 0x8464?0x8467 0x8548?0x854f 1010b 0x8468?0x846b 0x8550?0x8557 1011b 0x846c?0x846f 0x8558?0x855f 1100b 0x8470?0x8473 0x8560?0x8567 1101b 0x8474?0x8477 0x8568?0x856f 1110b 0x8478?0x847b 0x8570?0x8577 1111b 0x847c?0x847f 0x8578?0x857f button box formation please refer to the lm1247 datasheet for details. operation of the shadow feature please refer to the lm1247 datasheet for details. operation of the bordering feature please refer to the lm1247 datasheet for details. constant character height mechanism please refer to the lm1247 datasheet for details. LM1276 www.national.com 46
attribute table and enhanced features (continued) display window 1 to display window 2 spacing please refer to the lm1247 datasheet for details. evaluation character fonts the character font for evaluation of the LM1276 is shown in figure 19 through figure 26 , where each represents one of the 8 available rom banks. each bank is shown with in- creasing character address going from upper left to lower right. the actual font will depend on customer customization requirements. note that the first two character codes of the two-color font in rom bank 4 (0x00 and 0x01) are carried over from the lm1237 rom where they were reserved for the end-of- screen (eos) and end-of-line (eol) codes respectively. in the case of the LM1276, these two locations can be used for displayable characters as long as they are not needed when this bank is addressed from bank select register 0. if it is addressed from bank select registers 1, 2 or 3, then these two lower characters will be usable. please see the section ?end-of-line and end-of-screen codes?. similarly, the first two characters in any bank, which is ad- dressed from bank select register 0 will not be usable since those addresses will be interpreted as the eol and eos codes. 20096944 figure 19. rom bank 0 two color character font 20096945 figure 20. rom bank 1 two color character font LM1276 www.national.com 47
attribute table and enhanced features (continued) 20096946 figure 21. rom bank 2 two color character font 20096947 figure 22. rom bank 3 four color character font 20096948 figure 23. rom bank 4 two color character font LM1276 www.national.com 48
attribute table and enhanced features (continued) 20096949 figure 24. rom bank 5 two color character font 20096950 figure 25. rom bank 6 two color character font 20096951 figure 26. rom bank 7 four color character font LM1276 www.national.com 49
physical dimensions inches (millimeters) unless otherwise noted 20096968 national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications. for the most current product information visit us at www.national.com. life support policy national?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. banned substance compliance national semiconductor manufactures products and uses packing materials that meet the provisions of the customer products stewardship specification (csp-9-111c2) and the banned substances and materials of interest specification (csp-9-111s2) and contain no ??banned substances?? as defined in csp-9-111s2. leadfree products are rohs compliant. national semiconductor americas customer support center email: new.feedback@nsc.com tel: 1-800-272-9959 national semiconductor europe customer support center fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer support center email: ap.support@nsc.com national semiconductor japan customer support center fax: 81-3-5639-7507 email: jpn.feedback@nsc.com tel: 81-3-5639-7560 www.national.com LM1276 150 mhz i 2 c compatible rgb preamplifier with internal 512 character osd rom, 512 character ram and 4 dacs

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